Plasma and process damage can cause many forms of electrical degradation, observable at time zero as the finished wafer exits the fab. Additionally, latent reliability problems can be caused by plasma and process damage, which are undetectable by any normal parametric or product-level electrical testing. The reliability hazards potentially created or degraded by damage include all transistor failure modes, dielectric lifetime degradation, hot carrier lifetime, negative-bias instability, intermetal dielectric degradation, corrosion, and stress migration. Ongoing wafer-level reliability testing or a proxy such as a revealing stress is necessary to detect and analyze plasma and process-induced reliability degradation.