Design rules are an essential tool to minimize plasma and process damage. Design rules can prevent worst-case design and layout conditions, reducing the probability of damage. Design rules for wells and triple-wells can minimize damage from well coupling. Gate-related design rules can prevent antenna effects from damaging the transistors. Source and drain-related design rules can mitigate damage from source and drain antennas. Metallization layer design rules can minimize the backend of line antennas. Bond pad design rules are important as they form natural antennas. Specialized design rules can prevent damage to metal-insulator-metal capacitors. Technology-specific design rules for DRAMs, flash memories, and CMOS imagers are discussed.