This chapter surveys appropriate test structures for characterizing process and plasma damage. The test structure configuration and layout are described by process modules in a CMOS process flow. Transistor-related test structures include gate antennas, alternate transistor structures, structures without field edges, light-detecting structures, mismatch structures, source and drain antennas, ring oscillators, etc. Ion implant-related damage structures are described and discussed. CMOS wells and triple well-related structures are covered. Bond pad damage-related structures are reviewed. Specialized pad structures are described to allow plasma damage testing during processing.