Machine learning can be used to enhance chip design simulation. AI/ML can be applied to each step. In this chapter, we will discuss how ML can be deployed to enhance ASIC/FPGA design flow from EDA/simulation perspective and accelerate design and verification steps. The emergence of new technologies with unconventional requirements and Saturation of Moore’s law due to limitations of CMOS technology are motivators for deploying AI in EDA tools as recent advances in deep learning makes it a possible deployment. Deep learning stacks many hidden layers together, allowing for more sophisticated processing of training data. Moreover, it can extract the relevant features of any problem domain as at every layer, DL models use shift-invariant filters to perform convolution, followed by a non-linear operation such as rectified-linearity (ReLU). Any ML algorithm should be autonomous and generic.