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Dynamic Partial Reconfiguration is a powerful feature available in some FPGAs that enables the reconfiguration of specific regions within the FPGA fabric without halting the whole system. This capability opens new opportunities for more efficient utilization of the available FPGA resources since the hardware can be configured dynamically to better fit the demands of varying workloads. In this work, we investigate the Dynamic Partial Reconfiguration available from Xilinx/AMD FPGAs as Dynamic Function Exchange in multicore RISC-V systems, focusing on maximizing area utilization while minimizing execution time for a set of testbenches. This approach leverages the modularity of the RISC-V architecture that goes beyond the traditional customization provided by the RISC-V processor extensions. As a result for a testbench composed of CNN, Linked List, and Simplex Method, we could notice an improvement from 0.15% to 6% in execution time by dynamically reconfiguring the RISC-V in relation to the number of cores and configurations of each core regarding cache size and availability of FPU.

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Dynamic Function Exchange in FPGA to Redefine RISC-V Multicore Architectures at Runtime

  • 会议论文

  • 发表日期：

    2025年

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  • Téo Sobrino Alves,
  • Vanderlei Bonato

摘要

Dynamic Partial Reconfiguration is a powerful feature available in some FPGAs that enables the reconfiguration of specific regions within the FPGA fabric without halting the whole system. This capability opens new opportunities for more efficient utilization of the available FPGA resources since the hardware can be configured dynamically to better fit the demands of varying workloads. In this work, we investigate the Dynamic Partial Reconfiguration available from Xilinx/AMD FPGAs as Dynamic Function Exchange in multicore RISC-V systems, focusing on maximizing area utilization while minimizing execution time for a set of testbenches. This approach leverages the modularity of the RISC-V architecture that goes beyond the traditional customization provided by the RISC-V processor extensions. As a result for a testbench composed of CNN, Linked List, and Simplex Method, we could notice an improvement from 0.15% to 6% in execution time by dynamically reconfiguring the RISC-V in relation to the number of cores and configurations of each core regarding cache size and availability of FPU.