Wireless attacks targeting the Internet of Things (IoT) pose challenges to its security. To counter this threat, in-depth security mechanisms such as Intrusion Detection Systems (IDSs) are used. The implementation of IDSs in edge devices is challenging, considering the inherent constrained nature of IoT devices. In this paper, three Intrusion Detection System (IDS) implementation approaches, software, in-core hardware, and off-core hardware are defined and compared, using an IoT-context representative case study. Advantages and disadvantages of each approach are assessed and discussed, comparing design time, ease of maintenance, detection performance, and SoC resource consumption. Our results, relative to the SoC baseline, show that the software approach used \(17.92\%\) more energy consumption per packet ( \(+0.19 mJ/p\) ) than the hardware approach. Conversely, the hardware approach incurs a higher FPGA resource overhead, requiring up to \(12.06\%\) more LUT and \(7.75\%\) more FF.

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Comparison Between In-Core Hardware IDS, Off-Core Hardware IDS and Software IDS

  • Tianxu Li,
  • Mohamed El-Bouazzati,
  • Camille Monière,
  • Philippe Tanguy,
  • Guy Gogniat

摘要

Wireless attacks targeting the Internet of Things (IoT) pose challenges to its security. To counter this threat, in-depth security mechanisms such as Intrusion Detection Systems (IDSs) are used. The implementation of IDSs in edge devices is challenging, considering the inherent constrained nature of IoT devices. In this paper, three Intrusion Detection System (IDS) implementation approaches, software, in-core hardware, and off-core hardware are defined and compared, using an IoT-context representative case study. Advantages and disadvantages of each approach are assessed and discussed, comparing design time, ease of maintenance, detection performance, and SoC resource consumption. Our results, relative to the SoC baseline, show that the software approach used \(17.92\%\) more energy consumption per packet ( \(+0.19 mJ/p\) ) than the hardware approach. Conversely, the hardware approach incurs a higher FPGA resource overhead, requiring up to \(12.06\%\) more LUT and \(7.75\%\) more FF.