Low Density Parity Check (LDPC) codes under iterative decoding have shown remarkable error correction capabilities, with moderate complexity requirements. Initially, in this paper a check based on a part of the parity check matrix (core part check) is presented. The proposed check is amenable for hardware implementation and allows the termination of the decoding procedure at a sub-iteration level, i.e., within an iteration. In this way the number of clock cycles required reduced by 150 for the semi-parallel architecture and for 5G NR codes. Simultaneously the Block Error Rate (BLER) remains the same while hardware becomes simpler. In addition, this paper introduces a novel scheduling scheme combined with the core part check and a syndrome-select logic. Experimental results are offered, assuming the parallel architecture, which show that the proposed rescheduling reduces the average number of required clock cycles per decoded word. Simultaneously improves the BLER utilizing exactly the same hardware. Specifically, targeting 5G NR LDPC codes, gains of 35% are achieved, for both the OMS and NMS algorithms. Furthermore, an innovative approach for the merge network of the reconfigurable barrel shifter is proposed. Finally, an ASIC implementation for semi-parallel architecture and the energy consumption gained with the proposed algorithm are presented.