The BaSIC topology with a gate source shorted silicon depletion mode MOSFET (DMM) in series with the source electrode was shown to be effective for improving the short-circuit withstand time of a SiC power MOSFET in Chap. 5 . An alternative approach to improving the short-circuit withstand time for the SiC power MOSFET is by connecting a ballast resistance in series with the source electrode. The voltage drop across the ballast resistance during the short-circuit event will reduce the gate drive voltage for the SiC power MOSFET and bring down its saturation current level. This will increase the short-circuit withstand time. However, this approach will obviously increase the on-resistance and also the switching losses. A comparison of the BaSIC(DMM) topology with ballast resistance approach is performed in this chapter by using trade-off curves for the two approaches.