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The efficacy of the BaSIC topology for improving the short-circuit withstand time for SiC power MOSFETs was demonstrated in the previous chapter by using a gate source shorted silicon depletion mode MOSFET (DMM) in series with the source electrode. It is important to compare the BaSIC(DMM) topology with the alternative approach of reducing the gate bias. Reducing the gate bias for a power MOSFET brings down its saturation current level. This will increase the short circuit-withstand time. However, this approach also produces an increase in the on-resistance and switching losses. A comparison of the BaSIC(DMM) topology with gate bias reduction is performed in this chapter by using trade-off curves for the two approaches.

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BaSIC(DMM) Topology Versus Gate Bias Reduction

  • 章节

  • 发表日期：

    2025年

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  • B. Jayant Baliga,
  • Ajit Kanale

摘要

The efficacy of the BaSIC topology for improving the short-circuit withstand time for SiC power MOSFETs was demonstrated in the previous chapter by using a gate source shorted silicon depletion mode MOSFET (DMM) in series with the source electrode. It is important to compare the BaSIC(DMM) topology with the alternative approach of reducing the gate bias. Reducing the gate bias for a power MOSFET brings down its saturation current level. This will increase the short circuit-withstand time. However, this approach also produces an increase in the on-resistance and switching losses. A comparison of the BaSIC(DMM) topology with gate bias reduction is performed in this chapter by using trade-off curves for the two approaches.