This paper presents a comprehensive evaluation of three modified advanced neural network architectures-ResNet-34, EfficientNet-B0, and SqueezeNet-by measuring their accuracy in detecting and classifying defects in silicon wafer maps. The research utilized the WM-811K dataset, consisting of various defect types, to train and test each model under binary and multi-class classification scenarios. A customized image processing algorithm was developed to process the wafer map images, which were then used as inputs to the neural network models. The accuracy of these models was the primary metric used to assess their performance. In binary classification tasks, EfficientNet-B0 demonstrated the highest test accuracy of 94.6% with an average test accuracy of 93.2%. ResNet-34 followed closely with a test accuracy of 93.5% and an average test accuracy of 91.6%. SqueezeNet, while achieving a lower test accuracy of 92.6%, maintained an average test accuracy of 91.4%. For multi-class classification, EfficientNet-B0 again led with a test accuracy of 84.2% and an average test accuracy of 84.1%. ResNet-34 achieved a test accuracy of 83.1% with an average test accuracy of 82.3%, while SqueezeNet had a test accuracy of 82.9% and an average test accuracy of 79.7%. The paper further elaborates on the performance metrics of the models. It also discusses the current research and suggests areas for future work.