This chapter describes the design and implementation of a single-core 5-bit flash ADC operating at 18.5 GS/s. The ADC leverages a bulk-driven flash reference generation concept based on the dedicated comparator offset. This method highly suppresses the introduced kickback to the reference side resulting in a relaxed design and reduced power consumption compared to the conventional flash architecture using differential-difference amplifiers (DDAs). Furthermore, an UWB T&H has been adopted in this ADC. Since the implemented single-core design is intended for a 4X-time-interleaved (TI) flash ADC operating at 74 GS/s (18.5 GS/s per lane), the T&H requires to maintain a certain accuracy and ENOB (better than 5.5 bits ENOB) up to 37 GHz or the Nyquist frequency of the 74 GS/s ADC. To verify the sampling front-end (UWB T&H) performance prior to the flash ADC design, a stand-alone test chip including the T&H design has been implemented. Design and implementation of the stand-alone UWB T&H, as well as the characterization results, are discussed in Sect. 8.1. The complete 5-bit flash ADC core design using the aforementioned T&H core is discussed in Sect. 8.2 along with the flash ADC measurement results.