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Starting from comparative measurements over the 2–400 K temperature range of the main figures of merit (FoMs) of 28-nm and \(22\mbox{-}\mathrm {nm}\) FDSOI as a function of the back-gate voltage and of FinFET and SiGe heterostructure bipolar (HBT) transistors for analog-mixed-signal, mm-wave, high-speed digital, and fiberoptic circuits, we first develop analytical expressions for these FoMs as a function of the backgate voltage. Next we show how the back gate, unique to FDSOI technologies, can be used in conjunction with existing algorithmic design methodologies based on constant current density bias, previously developed for bulk CMOS circuits, to further optimize the performance of these circuits in terms of their FoMs, to extend it over the entire temperature range above, and to provide tuneability of most of these circuit FoMs without loading the signal path. Relevant examples, where the back gate features prominently in all these four classes of circuits, are covered from DC to 200 GHz and for bias current densities ranging from the deep subthreshold to very strong inversionstrong inversion regions.

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Maximizing the Figures of Merit, Temperature Range, and Optimizing the Algorithmic Design Methodologies Based on Constant Current Density Bias for FDSOI Analog-Mixed-Signal, Digital, mm-Wave, and Fiberoptic Circuits from the Back-Gate Voltage

  • 章节

  • 发表日期：

    2025年

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  • S. Bonen,
  • S. Pati Tripathi,
  • A. Bharadwaj,
  • J. McIntosh,
  • J. Zhao,
  • A. Zandieh,
  • M. S. Dadash,
  • S. Shopov,
  • M. J. Gong,
  • L. Wu,
  • U. Alakusu,
  • T. Jaeger,
  • G. Cooke,
  • T. Liu,
  • H. Y. Hsu,
  • S. P. Voinigescu

摘要

Starting from comparative measurements over the 2–400 K temperature range of the main figures of merit (FoMs) of 28-nm and \(22\mbox{-}\mathrm {nm}\) FDSOI as a function of the back-gate voltage and of FinFET and SiGe heterostructure bipolar (HBT) transistors for analog-mixed-signal, mm-wave, high-speed digital, and fiberoptic circuits, we first develop analytical expressions for these FoMs as a function of the backgate voltage. Next we show how the back gate, unique to FDSOI technologies, can be used in conjunction with existing algorithmic design methodologies based on constant current density bias, previously developed for bulk CMOS circuits, to further optimize the performance of these circuits in terms of their FoMs, to extend it over the entire temperature range above, and to provide tuneability of most of these circuit FoMs without loading the signal path. Relevant examples, where the back gate features prominently in all these four classes of circuits, are covered from DC to 200 GHz and for bias current densities ranging from the deep subthreshold to very strong inversionstrong inversion regions.