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This chapter describes the design and implementation of the first true voltage-mode VCSEL driver achieving 60 Gbit/s with bit error rate (BER) \({<}10^{-12}\) at peak efficiency of 0.36 pJ/bit. This approach improves the state-of-the-art by a factor of 1.9x. The concept of the back-gate is utilized here for fine-tuning the input impedance and the optical output signal amplitude, enabling robust performance without the need for additional equalization techniques. Experiments achieve error-free transmission of 56 Gbit/s over 100 m fiber. Furthermore, an advanced demonstration with Short Wavelength Division Multiplexing (SWDM) expands the data rate potential to 224 Gbit/s while maintaining an overall efficiency of 0.4 pJ/bit. These advancements highlight the potential of highly efficient VCSEL drivers for future high-speed optical links, addressing both power and bandwidth limitations in previous designs.

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Ultra-Low-Power Voltage-Mode VCSEL-Driver with Back-Gate Bias Tuning

  • 章节

  • 发表日期：

    2025年

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  • Urs Hecht,
  • Helia Ordouei,
  • Friedel Gerfers

摘要

This chapter describes the design and implementation of the first true voltage-mode VCSEL driver achieving 60 Gbit/s with bit error rate (BER) \({<}10^{-12}\) at peak efficiency of 0.36 pJ/bit. This approach improves the state-of-the-art by a factor of 1.9x. The concept of the back-gate is utilized here for fine-tuning the input impedance and the optical output signal amplitude, enabling robust performance without the need for additional equalization techniques. Experiments achieve error-free transmission of 56 Gbit/s over 100 m fiber. Furthermore, an advanced demonstration with Short Wavelength Division Multiplexing (SWDM) expands the data rate potential to 224 Gbit/s while maintaining an overall efficiency of 0.4 pJ/bit. These advancements highlight the potential of highly efficient VCSEL drivers for future high-speed optical links, addressing both power and bandwidth limitations in previous designs.