FPGA Realization of Neural Network Accelerator for Image Classification
摘要
Artificial intelligence systems are increasingly pervasive. As graph-based models grow in complexity, there is a pressing need for hardware architectures that minimize training and inference times. This work proposes a CNN (Convolutional Neural Network) accelerator designed to enhance CNN operations, providing faster and more efficient inference. The model will be implemented on an FPGA kit, with inference results transmitted via UART. Users configure the graph, train the model, and store the weights before deploying the trained CNN accelerator in a computer vision pipeline. This approach significantly boosts inference throughput while maintaining low power consumption, facilitating the deployment of complex architectures such as ResNet-50, ResNet-101, ResNet-152, YOLO, and VGG-17/19 on edge devices. Furthermore, implementing such application-specific hardware in data centers allows users to leverage cloud services at a reduced cost, benefiting both the cloud providers by attracting more users and the users by lowering their expenses.