In this paper, graphene nano ribbon (GNR) FET based dual output second generation current conveyor (DO-CCII) has been designed and simulated at 16 nm technology node using HSPICE. The performance of GNRFET based DO-CCII has been optimized by varying number of GNRs. Further, GNRFET DO-CCII is simulated at different channel length and width and observed that GNRFET DO-CCII shows the lowest power consumption 21.4 µWatt at 16 nm channel length and provide 128.5% reduction in power over 32 nm channel length and 378% reduction in power over 45 nm channel length and 1.7 nm width. Furthermore, GNRFET DO-CCII with 13 dimer lines offer 198.5% lower power consumption over GNRFET DO-CCII with 12 dimer lines at 16 nm channel length.