Scholarlink

The susceptibility of the register file to errors is a key concern in processor design for safety-critical applications, since it consists of a relatively vast matrix of flip-flop cells that hold data highly prone to common faults like Single Event Upsets. We present two practical methodologies for implementing information redundancy using Error-Correcting Code mechanisms within the register file, as an alternative to introduce classic Triple Modular Redundancy. We demonstrate the designs on the Klessydra processor core family, with particular reference to the fault-tolerant Klessydra-dfT03 core. These methods demonstrate how the micro-architectural characteristics of the core can be exploited along with the information protection characteristics, reducing the hardware occupation by about 14.47% and 32.85% in LUTs and FFs, respectively, without significantly degrading performance or increasing dynamic power consumption.

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Alternative Implementations of Error Correcting Codes in Register Files of a RISC-V Safety Critical Processor

  • 会议论文

  • 发表日期：

    2025年

查看全文
  • Marcello Barbirotta,
  • Marco Angioli,
  • Antonio Mastrandrea,
  • Abdallah Cheikh,
  • Francesco Menichelli,
  • Mauro Olivieri

摘要

The susceptibility of the register file to errors is a key concern in processor design for safety-critical applications, since it consists of a relatively vast matrix of flip-flop cells that hold data highly prone to common faults like Single Event Upsets. We present two practical methodologies for implementing information redundancy using Error-Correcting Code mechanisms within the register file, as an alternative to introduce classic Triple Modular Redundancy. We demonstrate the designs on the Klessydra processor core family, with particular reference to the fault-tolerant Klessydra-dfT03 core. These methods demonstrate how the micro-architectural characteristics of the core can be exploited along with the information protection characteristics, reducing the hardware occupation by about 14.47% and 32.85% in LUTs and FFs, respectively, without significantly degrading performance or increasing dynamic power consumption.