This chapter will review advances in metrology and device processing techniques to enable vertical GaN P-iN diodes. This will include a discussion on wafer metrology techniques as a means to evaluate both as-received wafers as well as epitaxial layers grown on wafers. Some such techniques include mercury probe mapping, optical profilometry, and X-ray techniques. We will provide an overview of each technique and an example of their application to GaN wafers. The second half of this chapter will address device processing. This will include a discussion on epitaxial layer design, device fabrication steps, edge termination processes, and process validation through device testing. Here we will focus specifically on application to vertical GaN P-iN diode architectures. Finally, we will provide a brief discussion of packaging and conclude the chapter.