As the volume and diversity of Internet of Things (IoT) data continues to grow, traditional cloud-based processing methods face significant challenges, including latency, bandwidth constraints, and privacy concerns. Our research focuses on employing decision trees (DTs) [1] as an intelligent filtering mechanism on the edge. We propose a novel programmable and scalable custom ASIC architecture designed for decision tree based Machine Learning (ML) inference. Each bit-slice incorporates two 8-bit SISO input registers connected to an 8-bit comparator for data processing, the output of the comparator drives the select line of Mux, which selects the respective true and false paths. Each bit-slice can be programmed into either a leaf node or a regular node. A leaf node stores classification labels. A regular node compares a feature value with a weight value to decide between true and false paths. Given a DT model, the decision tree can be pre-programmed to store the model weights in respective tree nodes. In the inference phase, feature values are sequentially fed into the DT nodes. After the feature values are loaded the DT tree performs an inference with the classification value generated in the root node. We have implemented and validated the architecture at the layout level using Cadence Virtuoso in 0.5  \(\upmu \) m CMOS technology node. A 5-level DT occupies roughly 90 mm \(^2\) area with 22.58 mW of power consumption at a maximum clock speed of 12.8 MHz.