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This paper introduces a proposal for implementing the Physical Link Layer of PCI Express in accordance with PCI Express 2.0 standards. PCI Express, a high-performance, point-to-point communication protocol, has revolutionized the world of data transfer by offering exceptional bandwidth, making it the go-to choose for a wide array of applications. Its layered architecture, consisting of three distinct layers, facilitates efficient data transfer through packet-based communication between the layers. Widespread use in various applications, including high-speed storage devices, graphics cards, and network cards. The work encompasses the design and verification of multiple physical layer blocks for PCI Express. These blocks are modeled using Verilog at the RTL level and verified using Questasim, a tool from Mentor Graphics.

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Design and Implementing a PCI Express Serdes Block Using HDL

  • 会议论文

  • 发表日期：

    2025年

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  • Ravali Meesa,
  • G. Surekha

摘要

This paper introduces a proposal for implementing the Physical Link Layer of PCI Express in accordance with PCI Express 2.0 standards. PCI Express, a high-performance, point-to-point communication protocol, has revolutionized the world of data transfer by offering exceptional bandwidth, making it the go-to choose for a wide array of applications. Its layered architecture, consisting of three distinct layers, facilitates efficient data transfer through packet-based communication between the layers. Widespread use in various applications, including high-speed storage devices, graphics cards, and network cards. The work encompasses the design and verification of multiple physical layer blocks for PCI Express. These blocks are modeled using Verilog at the RTL level and verified using Questasim, a tool from Mentor Graphics.