This paper presents a low-power 68.7 dB Signal-to-Noise-Distortion Ratio (SNDR) 8-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) using passive Noise-Shaping (NS) and the noise efficiency comparator for IoT applications. This NS technique is based on the cascade of integrator feed-forward (CIFF) structure, both quantization and kT/C noises have been reduced simultaneously by utilizing an infinite impulse response filter (IIR) and a finite impulse response filter (FIR). As a result, the NS structure minimizes the number of capacitors while still achieving a high Effective Number of Bits (ENoB) resulting in high resolution and minimal power consumption. The performance of the proposed NS SAR ADC has been verified through simulation in a 180 nm CMOS process, achieving an ENoB of 10.7-bit with an 8-bit SAR ADC. With an area of 0.17 mm2, the NS SAR ADC consumes 421 µW from a 1.8 V voltage supply to achieve a Signal-to-Noise Ratio (SNR) of 59.32 dB. The simulated results demonstrate that the proposed NS SAR ADC is an effective method for IoT applications.