In Chap. 2 , we mentioned that the FPGAs implemented in 7 nm technologies brought about the most significant changes to the programmable interconnect architecture in almost two decades. That something was bound to change should not come as a surprise, since experts have already anticipated a dramatic rise in wire resistance as technology scales beyond this point. Why does resistance increase? Intuition about this is given already by high-school physics: Resistance of a wire is \(\rho \frac {L}{W \times H}\) , where L, W, and H are, respectively, the wire’s length, width, and height. If transistor dimensions shrink, so must the width of the wires. However, the height must shrink as well, since there is a limit to the aspect ratio beyond which the structure would collapse. Even though high-school physics allows us to anticipate that problems with high resistance will arise, it does not allow us to predict when precisely they will become so pronounced as to call for a drastic change in architectural design. For that, more complex resistance models are required, taking into account phenomena such as line-edge-roughness and the characteristics of the barrier. In this chapter, we develop a framework for physical modeling of programmable interconnect architectures at advanced FinFET nodes, going down to 3 nm. The goal is to be able to analyze and explain the design choices of the latest commercial architectures, as well as to enable architectural exploration in advanced technologies that can anticipate future developments. In doing so, we adapt state-of-the-art wire and via resistance models, previously developed at IMEC, to fit the level of abstraction required for rapid FPGA architecture exploration.