This paper proposes a highly effective Feedthrough logic (FTL) that reduces latency and power consumption while enhancing the performance of arithmetic circuits in asynchronous pipeline designs. Without the need for intermediate inverters and with the added feature of pre-evaluating output before all input is legitimate, FTL can be cascaded in a domino-like fashion. Dual rail FTL and single rail FTL are used in combination to build the data paths. The Synchronizing Logic Gate (SLG)’s two rail FTL implementation is utilized to build a dependable critical data path. By identifying the critical data path, a static NOR is gate employed as a 1 bit completion detector to produce a done signal for the complete data path. Single rail FTL, which merely transmits data, is used to build non-critical data path. In comparison to domino logic circuits, the suggested system offers superior asynchronous pipeline performance with extremely low dynamic power consumption and low propagation delay. This study compares the power dissipation and latency of different types of logic, including Domino, Basic FTL, Modified FTL, and High performance FTL. The high performance FTL is particularly effective for high speed asynchronous pipelining design circuits.