The RISC-V instruction set architecture (ISA) is increasingly gaining traction as an open-source standard, enabling the development of a variety of processor designs. These designs are capable of addressing a broad spectrum of application needs, spanning from embedded systems to high-performance computing. The RISC-V ISA features a modular structure, offering a selection of base ISAs and standardized extensions for customization. In this work, we present the first and open-source extension of a SystemC TLM-based RISC-V Virtual Prototype (VP) which supports the RISC-V “P” Packed-SIMD Version 0.9.11-draft-20211209 called RV-VP \(^{2}\) . The RISC-V VP is an open-source simulation platform in SystemC TLM that supports RV32GC and RV64GC. The RISC-V VP is extended for the P-extension of the RISC-V for RV32 specification to focus on simulating embedded application scenarios. A total of 243 instructions are added in the RISC-V VP simulator, which belongs to the mandatory specification of P-extension for RV32. The extended RISC-V VP simulator is evaluated for different test cases; matrix multiplication, convolution, max-pooling, and fully connected layer, to demonstrate the efficiency of P-extension in comparison to base ISA. A convolution neural network called Lenet-5 is also used as a test case to compare performance with the base RV32IM. The results show a maximum speed-up of 5.87 \(\times \) and 2.97 \(\times \) when using P-extension for a 4-way (8-bit) SIMD and a 2-way (16-bit) SIMD for matrix multiplication respectively. For Lenet-5 a speed-up of 4.08 \(\times \) when using P-extension (4-way (8-bit) SIMD) was observed.