The main focus of this chapter is to showcase the physical implementation of hASIC using a commercial 65nm CMOS technology. It provides a more realistic assessment of the PPA overheads by presenting the physical implementation of the selected designs. The analysis includes large circuits with varying levels of obfuscation applied. Furthermore, it presents the final layouts for baseline and optimized variants. The optimized variants incorporate the techniques presented in the previous chapter, highlighting the improvements achieved through optimization.