Performance Comparison of 4T SRAM Cell Using Different Techniques at 32nm and 22nm Nodes for Portable Electronic Devices
摘要
SRAM (Static Random Access Memory) has become an indispensable component in various Very Large-Scale Integration (VLSI) chips due to its high storage density and fast access times. This has significantly contributed to the global VLSI industry. The research community has also shown a growing interest in SRAM, particularly in low-power and low-voltage memory systems. The design of SRAM has evolved, with advancements in technology and manufacturing processes. One such design is the 4T SRAM, which utilizes CMOS, Schmitt Trigger, and Adiabatic technology. This design has been implemented at 22nm and 32nm nodes, showcasing the continuous improvement in semiconductor technology. The simulation of the 4T SRAM design was conducted using the Tanner EDA Software, a widely used tool in the industry. The simulation results have shown improvements in both power consumption and delay, which are critical factors in the performance of memory systems. Overall, SRAM has played a vital role in advancing VLSI technology, enabling the development of more efficient and powerful electronic devices. The continuous research and development in SRAM design and technology will further enhance its capabilities and contribute to the future growth of the semiconductor industry.