Full adders are fundamental components of arithmetic circuits that perform binary addition. However, conventional full adder designs consume a significant amount of power, which limits their applications in low-power devices. This paper proposes a low power full adder design that uses the LECTOR technique to reduce the power consumption and improve the performance. The LECTOR technique employs a logic effort-based approach to optimize the transistor sizes and the gate-level structure of the full adder. We implement a 1-bit full adder using the LECTOR technique and compare it with other existing designs in terms of power, delay, and power-delay product. The results show that our proposed design achieves up to 40% reduction in power, 25% reduction in delay, and 55% reduction in power delay product compared to the conventional CMOS design. Our design offers a promising solution for low-power arithmetic circuits in various applications. This new full adder design brings a refreshing breeze of efficiency to the world of binary math, promising a brighter future for low power devices.