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In communication transmitters peak cancellation (PC) is one of the essential modules. The main objective of PC is to reduce the peak-to-average power ratio (PAPR) of the message signal. FPGA implementation of PC is widely used technique because of low power and delay nature of FPGA. FIR filters are in general used as PC in communication receiver which requires higher order filter increases the usage of resources in FPGA. IIR filter with lower order one choice of using PC in communication receiver. In this paper we proposed a new method of PC technique using lower order IIR filter. We outline the design principles for the IIR filter in the context of PC and delve into the FPGA implementation strategy, emphasizing resource optimization. The effectiveness of our proposed method is validated using the VIVADO tool. The implemented design of PC performance is compared with the standard methods. The proposed design of PC significantly reduces the delay with limited power consumption.

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FPGA Based Peak Cancellation for Efficient Communication Transmitters

  • 会议论文

  • 发表日期：

    2025年

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  • G. Prasanna Kumar,
  • M. Pavan,
  • M. Sobha Rani,
  • K. V. Ganesh,
  • M. Narasimha Rao,
  • N. Yoshith

摘要

In communication transmitters peak cancellation (PC) is one of the essential modules. The main objective of PC is to reduce the peak-to-average power ratio (PAPR) of the message signal. FPGA implementation of PC is widely used technique because of low power and delay nature of FPGA. FIR filters are in general used as PC in communication receiver which requires higher order filter increases the usage of resources in FPGA. IIR filter with lower order one choice of using PC in communication receiver. In this paper we proposed a new method of PC technique using lower order IIR filter. We outline the design principles for the IIR filter in the context of PC and delve into the FPGA implementation strategy, emphasizing resource optimization. The effectiveness of our proposed method is validated using the VIVADO tool. The implemented design of PC performance is compared with the standard methods. The proposed design of PC significantly reduces the delay with limited power consumption.