The latency and complexity of decoders are critical to performance of devices such as memory and buffers. The number of locations to be accessed in an address could be in billions. We propose a multidimensional parallel decoder that divides the address space into multiple of smaller dimensions each is decoded separately in parallel. The decoding of a much smaller address is simpler compared to the decoding of the whole address space. A combinational circuit combines the outputs of the smaller numbers of decoded outputs that correspond to the different dimensions to obtain the full decoded address space. We also purpose a time multiplexed decoder that divides the address to multiple dimensions in time and uses the multidimensional parallel decoder to obtain the decoded outputs. The results of the multidimensional parallel decoder show reduction in the cost of implementation and latency by multiple folds compared to the conventional decoder.