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In sub-10-nm nodes, interconnect challenges increasingly impact SRAM subarray design, with rising resistance and capacitance (RC) in bitlines (BL) and wordlines (WL) leading to write failures. The previous chapter mitigates write failures issues by incorporating divided WL (DWL) and divided BL (DBL) techniques into 14-Å nanosheet-based SRAM subarrays design. However, these techniques introduce additional logic gates, which can increase macro-area and degrade macro-level power, performance, and area (PPA) metrics. To address this, the active interconnect (AIC) design is proposed, relocating logic gates to the back-end-of-line (BEOL) layer using 3D stacking and carbon nanotube (CNT) transistor technology. This solution significantly reduces subarray area penalties while improving subarray-level power and performance. Additionally, SRAM macros based on the AIC technique with CNT technology show a 65% improvement in macro-level energy–delay–area product (EDAP) as compared to the standard design. The study assesses different subarray designs (standard, divided, and AIC divided) and explores the potential of AIC for future SRAM subarray designs.

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SRAM Hierarchical Subarray Design with Active Interconnect Technique

  • 章节

  • 发表日期：

    2025年

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  • Hsiao-Hsuan Liu,
  • Francky Catthoor

摘要

In sub-10-nm nodes, interconnect challenges increasingly impact SRAM subarray design, with rising resistance and capacitance (RC) in bitlines (BL) and wordlines (WL) leading to write failures. The previous chapter mitigates write failures issues by incorporating divided WL (DWL) and divided BL (DBL) techniques into 14-Å nanosheet-based SRAM subarrays design. However, these techniques introduce additional logic gates, which can increase macro-area and degrade macro-level power, performance, and area (PPA) metrics. To address this, the active interconnect (AIC) design is proposed, relocating logic gates to the back-end-of-line (BEOL) layer using 3D stacking and carbon nanotube (CNT) transistor technology. This solution significantly reduces subarray area penalties while improving subarray-level power and performance. Additionally, SRAM macros based on the AIC technique with CNT technology show a 65% improvement in macro-level energy–delay–area product (EDAP) as compared to the standard design. The study assesses different subarray designs (standard, divided, and AIC divided) and explores the potential of AIC for future SRAM subarray designs.