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SRAM plays a vital role in system-on-chip designs, significantly impacting power, performance, and area (PPA). As the demand for larger last-level caches (LLCs) and improved on-die SRAM density rises, scaling challenges become more evident. This chapter explores bitcell area scaling, with a focus on 5-Å-compatible (A5) and 3-Å-compatible (A3) technology nodes. The complementary field-effect transistor (CFET) technology, featuring a vertically stacked architecture, presents promising advancements for CMOS scaling in sub-3-nm nodes by enabling significant reductions in cell height compared to nanosheet and forksheet technologies. However, scaling introduces key challenges, particularly in gate-cut (GC) dimensions and middle-end-of-line routing. This chapter investigates these issues, especially the limitations caused by substantial GC requirements and the bottlenecks in GC scaling. To address these challenges, we propose using dielectric isolation wall (DIW) instead of GC to separate gates in CFET SRAM bitcell designs, resulting in up to 17% bitcell area reduction. Despite these advancements, aggressive bitcell area scaling leads to increased routing complexity, limiting the potential power and performance (PP) gains across nodes. This chapter provides strategies to mitigate these challenges and optimize SRAM designs for future technology nodes.

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Sequential and Monolithic CFET SRAM Bitcell Designs with Stacked Fin, NS, and FS Channels Towards A3

  • 章节

  • 发表日期：

    2025年

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  • Hsiao-Hsuan Liu,
  • Francky Catthoor

摘要

SRAM plays a vital role in system-on-chip designs, significantly impacting power, performance, and area (PPA). As the demand for larger last-level caches (LLCs) and improved on-die SRAM density rises, scaling challenges become more evident. This chapter explores bitcell area scaling, with a focus on 5-Å-compatible (A5) and 3-Å-compatible (A3) technology nodes. The complementary field-effect transistor (CFET) technology, featuring a vertically stacked architecture, presents promising advancements for CMOS scaling in sub-3-nm nodes by enabling significant reductions in cell height compared to nanosheet and forksheet technologies. However, scaling introduces key challenges, particularly in gate-cut (GC) dimensions and middle-end-of-line routing. This chapter investigates these issues, especially the limitations caused by substantial GC requirements and the bottlenecks in GC scaling. To address these challenges, we propose using dielectric isolation wall (DIW) instead of GC to separate gates in CFET SRAM bitcell designs, resulting in up to 17% bitcell area reduction. Despite these advancements, aggressive bitcell area scaling leads to increased routing complexity, limiting the potential power and performance (PP) gains across nodes. This chapter provides strategies to mitigate these challenges and optimize SRAM designs for future technology nodes.