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In modern system-on-chip designs, SRAM caches account for a significant portion of the die area, often exceeding 50%. As cache size and core count continue to increase with each generation, the need to improve SRAM density becomes crucial for optimizing performance and power efficiency, especially in ultra-scaled nodes. This chapter presents an overview of the research background, motivation, and structure, providing insights into future scaling trends and challenges in SRAM design.

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Introduction

  • 章节

  • 发表日期：

    2025年

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  • Hsiao-Hsuan Liu,
  • Francky Catthoor

摘要

In modern system-on-chip designs, SRAM caches account for a significant portion of the die area, often exceeding 50%. As cache size and core count continue to increase with each generation, the need to improve SRAM density becomes crucial for optimizing performance and power efficiency, especially in ultra-scaled nodes. This chapter presents an overview of the research background, motivation, and structure, providing insights into future scaling trends and challenges in SRAM design.