This paper presents the architecture design, verification, and optimization of a SPI (Serial Peripheral Interface) Master, based on the specifications stated in SPI-block guide V03.06 by Motorola. Transferring serial data between a master and a slave device is possible via the synchronous protocol known as SPI. This work proposes high-speed SPI Master Block Design, Verification, and Optimization in terms of power. Reliability and manufacturing yield are greatly impacted by power. For ASIC/FPGA designers, power minimization is increasingly becoming a crucial design requirement. By addressing power at the RTL and system levels, power can be reduced. At these levels, sequential adjustments such as voltage/frequency scaling, power gating, sequential clock gating, and other micro-architectural approaches can be applied to reduce power and energy consumption. The primary goal of this paper is power reduction at the RTL using Clock gating technique. The whole design is created in Verilog using Xilinx Vivado software is used to verify the design Simulation and performance. Implemented design has 26.05% reduction in power dissipation and Slight increment in logic resources due to Area and power trade off. It also provides all the requirements of the SPI protocol in terms of modularity and functionality.