In today’s modern world, the number of transistors on a chip is increasing, leading to heightened circuit complexity. Consequently, careful consideration is essential during the design and verification processes. In the Register Transfer Logic (RTL) stage, designing and verifying are pivotal aspects of the overall design. To identify errors at the RTL level, Spyglass is utilized. This paper focuses on Spyglass, designed to analyze RTL code early in the digital design process, aiming to identify potential issues, enhance code quality, and optimize the design before progressing to subsequent stages of the design flow. Early detection of design issues facilitates faster iterations and improved design quality. This RTL verification method is employed to uncover bugs and errors in the design before synthesis. The optimization capabilities of Spyglass contribute to enhanced performance and increased overall design efficiency.