Short channel effects (SCEs) have become a critical concern with the continued scaling of semiconductor devices. It is suitably known that multiple gate control over channel in FinFET plus thin Si body results into lower SCEs and so it has replaced traditional MOSFET in nanometer region. In our work, we have come up with a comprehensive investigation of SCEs in both traditional MOSFET and emerging FinFET structures using SPICE simulation tool. The objective of this study is to analyze as well as compare the impact of short channel effects over device performance in these two distinct transistor technologies. Simulation-based study carried out in the work is majorly focused on various SCEs, including (DIBL) drain-induced barrier lowering, VT roll-off and (SS) subthreshold swing or MOSFETs and FinFETs. To demonstrate, impact of scaling gate length on various parameters of SCEs gate length of FINFET device is altered in the range of 20–7 nm. Through simulations, in this work, we show validation of performance benefits of FinFETs over MOSFET at distinct nanoscale technology nodes. The findings of our work provide valuable knowledge of the SCEs phenomena particularly in FinFET device at recently used technology node of 7 nm in the fabrication process.