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This paper investigates the integration of SIMT and scalar cores using the RISC-V based Vortex GPGPU. Initially, we detail a conventional integration with Purdue’s SoCET SoC AFTx07 that follows the standard host-device CPU-GPU model found in contemporary products. Subsequently, we propose two innovative architectures designed to address control flow divergence, which impedes efficiency in parallel computing by causing threads to follow divergent execution paths. The first architecture introduces a system where threads are statically prioritized based on degrees of divergence: high-priority threads (highly divergent) are allocated to a scalar core, and lower-priority (less divergent) ones to the SIMT core, based on modifications to the Vortex GPU. Although preliminary results show improved performance for scalar core threads, the static nature of thread priority assignment results in unpredictable performance enhancements due to the scheduler’s limited foresight on runtime fluctuations of thread divergence. The second architecture, currently under development, proposes a mechanism for runtime thread migration, setting a foundation for a system capable of adjusting to runtime conditions. A future, conceptual third architecture aims to dynamically assess the divergence of each thread, optimizing the integration of SIMT and scalar cores for advanced computing. This progression outlines a strategic approach to mitigate control flow divergence, promising a significant leap towards achieving higher efficiency in parallel processing systems.

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Integrating RISC-V SIMT and Scalar Cores: Loosely to Tightly Coupled

  • 会议论文

  • 发表日期：

    2025年

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  • Sooraj Chetput,
  • Anusuya Nallathambi,
  • Spencer Bowles,
  • Justin Cambridge,
  • Alex Chitsazzadeh,
  • Gagan Gundala,
  • Zengxiang Han,
  • Johnathan Hong,
  • Guilliame Hu,
  • Ronit Nallagatla,
  • Ansh Patel,
  • Khoi Pham,
  • Abinands Ramshanker,
  • Htet Yan,
  • FangLing Zhang,
  • Zach Lagpacan,
  • Clay Hughes,
  • Kevin Pedretti,
  • Mark Johnson,
  • Timothy G. Rogers

摘要

This paper investigates the integration of SIMT and scalar cores using the RISC-V based Vortex GPGPU. Initially, we detail a conventional integration with Purdue’s SoCET SoC AFTx07 that follows the standard host-device CPU-GPU model found in contemporary products. Subsequently, we propose two innovative architectures designed to address control flow divergence, which impedes efficiency in parallel computing by causing threads to follow divergent execution paths. The first architecture introduces a system where threads are statically prioritized based on degrees of divergence: high-priority threads (highly divergent) are allocated to a scalar core, and lower-priority (less divergent) ones to the SIMT core, based on modifications to the Vortex GPU. Although preliminary results show improved performance for scalar core threads, the static nature of thread priority assignment results in unpredictable performance enhancements due to the scheduler’s limited foresight on runtime fluctuations of thread divergence. The second architecture, currently under development, proposes a mechanism for runtime thread migration, setting a foundation for a system capable of adjusting to runtime conditions. A future, conceptual third architecture aims to dynamically assess the divergence of each thread, optimizing the integration of SIMT and scalar cores for advanced computing. This progression outlines a strategic approach to mitigate control flow divergence, promising a significant leap towards achieving higher efficiency in parallel processing systems.