The need to improve efficiency in DC–DC converters in embedded systems has triggered, in recent years, the exploration of new conversion topologies. Particularly, switch capacitor converters (SCCs) have gained traction in the industry due to their intrinsic higher efficiency when operated close to their natural conversion ratio. However, SCCs need a way to efficiently control their input voltage to provide fine regulation of the output. Any other regulation method would cause an increase in their losses and a drop in efficiency. A switch inductor converter (SIC), on the contrary, can provide fine regulation at the output by means of the control of the duty cycle and therefore can provide good efficiency over a wider span of conversion ratios. However, the maximum attainable efficiency (MAE) is limited by the performance of the inductor that, particularly in the mobile space, suffers of high series resistance (DCR) and high core and AC losses due to its small size and thickness. In an attempt to benefit from the advantages of both architectures, new hybrid topologies have been recently explored. This chapter illustrates a systematic approach to analyze the maximum attainable efficiency of a SIC or hybrid converter and provide tools to compare different topologies under the same conversion ratio and power level. It will compare the classic Two-Level buck topology with the Three-Level buck (3LB) (Kim et al., IEEE J Solid State Circuits 47(1): 206–219, 2012; Zheng et al., J Circuits Syst Comput 29(1), 2020) and a hybrid two-level buck with switched capacitor (Haug, 72 V hybrid DC-to-DC converter reduces intermediate bus converter size by up to 50%, Analogue Dialog) (2LB-CP) that combines a voltage cap divider with a two-level SIC buck converter.