In this chapter, we review the architectures of state-of-the-art analog and digital fractional-N PLL for Wi-Fi applications. For the sake of clarity, we briefly discuss the definition of phase difference, and we present circuitry to “extract” or “digitize” it. Then, we focus on fractional-frequency dividers. In particular, we derive the block diagram of a Digital-to-Time-Converter (DTC)-based fractional-frequency divider from basic phase definitions and timing diagrams. We show how a DTC-based fractional-frequency divider can be seen as a combination of phase pattern generation and addition. Then, we identify the operations of phase pattern generation and addition in the architectures of state-of-the-art analog/digital sampling/subsampling and TDC-based and Time-Arithmetic-Unit-based PLLs. The goal is to offer a unifying perspective to properly compare the PLL architectures in terms of design challenges and opportunities. Finally, state-of-the-art PLL designs from literature are compared in terms of their spur and phase noise performance.