Signoff timing analysis is a crucial final check for tapeout-ready designs, providing references for iterative Engineering Change Orders (ECOs). Obtaining SPICE-accurate timing information involves timing engines with substantial turnaround times, exacerbated by the growing number of corners and scenarios in advanced technology nodes. The complexity is heightened by intricate RC networks and parasitics. As interconnect delay surpasses gate delay in timing paths, rapid and precise interconnect delay estimation is essential. Recent advancements have highlighted the potential role of machine learning (ML) for predicting timing across various stages of the design flow. Despite these promising results, current ML-based methods for estimating interconnect delays often depend on labor-intensive feature extraction and can face runtime challenges, especially with large and complex RC networks. To address these challenges, this chapter proposes using graph learning to estimate wire timing during signoff. Specifically, it employs global message passing graph representation learning directly on RC graphs, enabling ultrafast net delay estimation without the need for extra features. Preprocessed graph features are used to improve accuracy with only a slight increase in runtime. The model supports cross-corner timing signoff, requiring only one known corner for accurate prediction of all remaining unknown corners. Evaluation across two industry technology nodes demonstrates superior runtime and accuracy under both single-corner and cross-corner conditions compared to recently proposed ML-based signoff interconnect delay estimators.