The widespread use of application-specific integrated circuits imposes rigorous demands on the design flow. One crucial aspect of the design is achieving timing closure. Timing violations cause reiterations in the flow, potentially revisiting the register-transfer level (RTL) design. Analyzing timing at RTL would enable earlier design choices and prevent violations later in the design process. However, this is costly, involving synthesis and timing analysis runs. Back-annotating an RTL design with timing information is challenging, as RTL boundaries may not be preserved in the synthesized netlist. Related works estimate timing metrics using ML but employ gate-level netlists as inputs. This chapter introduces an AI-enabled static timing analysis (STA) that utilizes an RTL intermediate representation (IR) as input and AI models to approximate pin-to-pin delays and slews. Estimated values are inputs to a block-based STA flow. The fine-grain integration of a classical approach for STA with AI models provides an excellent method for identifying RTL blocks that could be optimized. Timing-driven micro-architecture search can be further automated using transformation mechanisms of RTL generation tools and optimization algorithms. This flow could lead to an optimal RTL IR, providing a right-at-first RTL and reducing timing violations at later stages of the design flow.