This chapter presents our investigation of Premature edge breakdownPEBpremature edge breakdown in standard Complementary metal-oxide semiconductor (CMOS) CMOS single-photon Avalanche avalanche diodes. Here, standard Complementary metal-oxide semiconductor (CMOS) CMOS means single-well p-type Complementary metal-oxide semiconductor (CMOS) CMOS processes, which are not configured for imaging applications. Our goal is to demonstrate that high-performance SPADs can be obtained in the simplest of processes, without the need for special layers or specialized device engineering. Particularly, we report on the breakdown characteristics of a single-photon Avalanche avalanche diode structure fabricated in a \(0.5~\mu \mathrm {m}\) single-well Complementary metal-oxide semiconductor (CMOS) CMOS process. We investigated two mechanisms for preventing PEB. The first mechanism consists of using the lateral diffusion of adjacent n-wells to reduce the electric field at the diode’s periphery, and the second makes use of a polysilicon gate over the high-field regions to modulate the electric field. We studied each technique independently as well as their combined effect on the devices’ Avalanche avalanche profiles. In addition to marked alterations in the current-voltage curves near and above breakdown, the diodes’ breakdown voltages were increased by more than \(4 \mathrm {~V}\) , indicating that perimeter breakdown was curtailed. We found that the field gate method, which we have called Perimeter gatingperimeter gating, yields the best results, independent of n-well lateral diffusion. The chapter also presents a unified equivalent circuit model for perimeter gating and its use in Geiger mode Geiger-mode readout front-end design and simulation. This chapter is largely based on its related publications (Dandin et al., IEEE Sensors J. 10(11), 1682–1690 (2010) and Dandin et al., IEEE Sensors J. 16(9), 3075–3083 (2016)), Copyright, IEEE.