<p>In this work, a methodology to perform industrial customized wafer dose patterning on CMOS devices integrated in a flash technology is presented. The first step consists of a “corner-like” process at the wafer level to determine the sensitivity of the MOS saturation current (<i>I</i>_dsat) to pocket implant doses using parametric testing (PT) and the sensitivity of Ring Oscillator (RO) frequency to pocket implant doses using electrical wafer sorting (EWS). The second step is the generation of customized wafer dose pattern based on comprehensive PT or EWS full stacked data maps. Sensitivity estimation for both strategies will be provided. The last step is the optimization of implantation parameters to improve pattern accuracy. The advantages and disadvantages of all these methods will be compared and discussed.</p> Graphical abstract <p></p>