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<p>As interconnect dimensions scale to the nanometer regime in VLSI, geometric variability critically affects timing and power integrity. This study analyses Cu-SWCNT and coupled Cu-SWCNT interconnects using parametric and corner analysis to assess performance under dimensional fluctuations. An RLC model incorporating quantum resistance, kinetic inductance, and quantum capacitance is employed at the 14&#xa0;nm technology node. Results reveal that coupled interconnects exhibit higher variability due to capacitive crosstalk with width and spacing as dominant factors. The proposed approach offers insights for designing variability-tolerant Cu-SWCNT interconnects for future high-speed, low-power VLSI systems.</p> Graphical abstract <p></p>

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Corner and parametric analysis of process-induced variability in Cu-CNT interconnects for high performance integrated circuits

  • 期刊论文

  • 发表日期：

    2026年7月6日

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  • K. Seshasai,
  • P. Uma Sathyakam,
  • Kavicharan Mummaneni

摘要

As interconnect dimensions scale to the nanometer regime in VLSI, geometric variability critically affects timing and power integrity. This study analyses Cu-SWCNT and coupled Cu-SWCNT interconnects using parametric and corner analysis to assess performance under dimensional fluctuations. An RLC model incorporating quantum resistance, kinetic inductance, and quantum capacitance is employed at the 14 nm technology node. Results reveal that coupled interconnects exhibit higher variability due to capacitive crosstalk with width and spacing as dominant factors. The proposed approach offers insights for designing variability-tolerant Cu-SWCNT interconnects for future high-speed, low-power VLSI systems.

Graphical abstract