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<p>This paper presents a master–slave (MS) flip-flop design that employs a single-phase clock and a mixed latch topology, utilizing only 19 transistors (13 NMOS and 6 PMOS) to achieve ultra-low power consumption and high-speed operation. The proposed flip-flop is designed to minimize clock-to-Q (TCQ) delay, average power dissipation, and leakage current, making it suitable for energy-efficient VLSI systems. It was implemented in a 45&#xa0;nm technology node and evaluated under process-voltage-temperature (PVT) variations, temperature fluctuations, and Monte Carlo simulations to verify robustness and reliability. Post-layout analysis confirmed the design’s correctness through successful Design Rule Check (DRC) and Layout Versus Schematic (LVS) verification, with a compact area of 19.106&#xa0;μm². Furthermore, for fair comparison, both the proposed and baseline flip-flop designs were implemented using the same 90&#xa0;nm CMOS technology in the Cadence Virtuoso environment. Compared to the Adaptive Data Track Flip-Flop (ADTFF), the proposed design achieves a 13.24% reduction in TCQ delay and a 37.19% reduction in average power, demonstrating its effectiveness for low-power, high-performance digital applications.</p>

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19-transistor single-phase clocking master-slave flip-flop with mixed topology

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年1月5日

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  • Dhandapani Vaithiyanathan,
  • Swatantrata Shukla,
  • Preeti Verma,
  • Komal Gupta,
  • Alok Kumar Mishra,
  • Baljit Kaur

摘要

This paper presents a master–slave (MS) flip-flop design that employs a single-phase clock and a mixed latch topology, utilizing only 19 transistors (13 NMOS and 6 PMOS) to achieve ultra-low power consumption and high-speed operation. The proposed flip-flop is designed to minimize clock-to-Q (TCQ) delay, average power dissipation, and leakage current, making it suitable for energy-efficient VLSI systems. It was implemented in a 45 nm technology node and evaluated under process-voltage-temperature (PVT) variations, temperature fluctuations, and Monte Carlo simulations to verify robustness and reliability. Post-layout analysis confirmed the design’s correctness through successful Design Rule Check (DRC) and Layout Versus Schematic (LVS) verification, with a compact area of 19.106 μm². Furthermore, for fair comparison, both the proposed and baseline flip-flop designs were implemented using the same 90 nm CMOS technology in the Cadence Virtuoso environment. Compared to the Adaptive Data Track Flip-Flop (ADTFF), the proposed design achieves a 13.24% reduction in TCQ delay and a 37.19% reduction in average power, demonstrating its effectiveness for low-power, high-performance digital applications.