Abstract <p>This work presents a comprehensive simulation-based analysis of impact of fringing fields originating from spacer dielectrics on the electrostatic and analog/Radio Frequency (RF) characteristics of Graded Channel Junctionless Gate-All-Around Metal Oxide Field Effect Transistor (GC-JL-GAA-MOSFET). Using the Silvaco ATLAS device simulator, we investigate the device behavior under different spacer dielectric materials – specifically Air (<i>K</i> = 1), SiO₂ (<i>k</i> = 3.9), Al₂O₃ (<i>k</i> = 9.3), and HfO₂ (<i>k</i> = 22). The novelty lies in integrating graded channel doping with systematic spacer engineering – tracking both electrostatic performance and analog/RF metrics. Simulation results reveal that increasing ksp significantly reduces the OFF-state current (<i>I</i>_OFF) from 5.9 × 10⁻¹³ A (for Air) to 5.2 × 10⁻¹⁵ A (for HfO₂), while maintaining a high ON-state current (<i>I</i>_ON) of the order of 10^–5 A. The I_ON/I_OFF ratio improves from 4.2 × 10⁷ to 2.3 × 10⁹, indicating enhanced switching performance. Additionally, subthreshold swing (SS) drops from 65.5 to 61.5&#xa0;mV/dec, and Drain Induced Barrier Lowering (DIBL) improves from 22.4 to 4.1 mV/V with high-<i>k</i>_sp materials. In the analog domain, transconductance (<i>g</i>_m) rises from 0.9 × 10^–5 S to 2 × 10^–5 S and intrinsic gain (<i>A</i>_V) from 25 to 40 dB. RF analysis shows that significant improvements are observed in Transconductance Frequency Product (TFP), Gain Frequency Product (GFP), and Gain Transconductance Frequency Product (GTFP). These results marked enhancement in key metrics due to spacer engineering. The study demonstrates that high-<i>k</i>_sp spacers can be an effective design knob for tuning both digital and analog/RF characteristics in next-generation nano-scale Graded Channel Junctionless Gate-All-Around Metal Oxide Field Effect Transistors (GC-JL-GAA- MOSFET).</p>