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Abstract <p>The optimal regime of trap reach—high resistivity (TR-HR) layer formation—was developed by the CO<sup>+</sup> ion implantation (<i>E</i> = 90–200 keV, <i>F</i> = (0.3–3.0) × 10<sup>16</sup> cm<sup>–2</sup>) and subsequent furnace or rapid thermal annealings (FA or RTA). The TR-HR zones in Si substrates can be placed under microwave or photon radiation in silicon-on-insulator (SOI) radiophotonic integral circuits (RPIC) based on both standard SOI SiO<sub>2</sub> buried oxide (BOX) up to 1 µm thick and on SOI wafers with a crystalline high-k BOX with an equivalent oxide thickness (EOT) ≥1 nm. The TR-HR layer during the stepwise RTA (sRTA) at 700 to 950°C reduced the BOX thickness and increased the effective EOT, but, at the same time, provided the highest decrease in the pass-through capacity <i>C</i><sub>p</sub> and an increase in the effective substrate resistance ρ<sub>eff</sub>, similar to high-resistance TR-HR SOI® wafers.</p>

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UTBB SOI-Structures with Local TR-HR Ultrahigh-Resistance Layers for Radio-Photonic Integrated Circuits

  • 期刊论文

  • 发表日期：

    2025年12月1日

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  • V. P. Popov,
  • V. E. Zhilitskii,
  • V. A. Antonov,
  • L. N. Safronov,
  • A. V. Miakonkikh,
  • K. V. Rudenko

摘要

Abstract

The optimal regime of trap reach—high resistivity (TR-HR) layer formation—was developed by the CO+ ion implantation (E = 90–200 keV, F = (0.3–3.0) × 1016 cm–2) and subsequent furnace or rapid thermal annealings (FA or RTA). The TR-HR zones in Si substrates can be placed under microwave or photon radiation in silicon-on-insulator (SOI) radiophotonic integral circuits (RPIC) based on both standard SOI SiO2 buried oxide (BOX) up to 1 µm thick and on SOI wafers with a crystalline high-k BOX with an equivalent oxide thickness (EOT) ≥1 nm. The TR-HR layer during the stepwise RTA (sRTA) at 700 to 950°C reduced the BOX thickness and increased the effective EOT, but, at the same time, provided the highest decrease in the pass-through capacity Cp and an increase in the effective substrate resistance ρeff, similar to high-resistance TR-HR SOI® wafers.