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Abstract <p>In this paper, a linear-in-dB digitally controlled variable gain low-noise amplifier (D-VGLNA) designed in 65 nm CMOS process for the 5G mm-wave phase-array subsystem is presented. Based on the current steering technique, the designed 8-bit D-VGLNA achieves a gain range of 22 dB from –12 to +10 dB while it consumes 9.6 mW (without buffers). By boosting up the input transconductance thanks to a cross-coupled technique, the designed D-VGLNA achieves a noise figure of 2.3 dB, and 7 dB at maximum and 0 dB gain, respectively. It shows an input-output phase shift insensitivity to gain setting thanks to parasitic capacitance mitigation by holding the parasitic capacitance at common junction cascode transistor constant during gain setting. The DVGLNA returns a maximum of –6.5 dBm of 1dB compression point.</p>

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A 2.3 dB NF 8-Bit Digitally-Controlled Variable Gain Low-Noise Amplifier for 5G Millimeter-Wave Beam-Former in 65 nm CMOS Process

  • 期刊论文

  • 发表日期：

    2025年8月1日

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  • Sid Ahmed Tedjini,
  • Sonia Salhi

摘要

Abstract

In this paper, a linear-in-dB digitally controlled variable gain low-noise amplifier (D-VGLNA) designed in 65 nm CMOS process for the 5G mm-wave phase-array subsystem is presented. Based on the current steering technique, the designed 8-bit D-VGLNA achieves a gain range of 22 dB from –12 to +10 dB while it consumes 9.6 mW (without buffers). By boosting up the input transconductance thanks to a cross-coupled technique, the designed D-VGLNA achieves a noise figure of 2.3 dB, and 7 dB at maximum and 0 dB gain, respectively. It shows an input-output phase shift insensitivity to gain setting thanks to parasitic capacitance mitigation by holding the parasitic capacitance at common junction cascode transistor constant during gain setting. The DVGLNA returns a maximum of –6.5 dBm of 1dB compression point.