Low-Power 9T SRAM Cell with Expanded Noise Margin in Near Subthreshold Region
摘要
This paper presents a 9T static random access memory (SRAM) cell designed and simulated for moderate performance and low-power applications. The proposed 9T cell shows commendable reduction in power dissipation while sustaining better stability. Various design metric parameters like read power, write power, read static noise margin (RSNM), write static noise margin (WSNM), read current, Ion/Ioff ratio are investigated. The proposed 9T SRAM cell is verified with the help of cadence virtuoso software using the 45 nm Generic Process Design kit module. The achieved simulated results are deeply investigated and compared with available state of art referenced SRAM cells. The finding show that the read power and write power of the proposed 9T SRAM cell is reduced by 1.46× and 1.37× respectively as compared to the conventional 6T SRAM cell. The RSNM and WSNM of the proposed 9T cell are enhanced by 1.94× and 1.2× as of 6T SRAM cell. This improvement in RSNM is obtained due to single-ended read operation. Further, the write and read access time become better by 1.08× and 1.10× as of the 6T SRAM cell. In addition to this, the proposed circuit shows the write and read energy are 3.3 and 114 aJ respectively, which are lowest as compared to the conventional 6T, tunable access 8T (TA8T), 11T, differential data-dependent power supplied 11T (D2P11T) SRAM cells.