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<p>Combinatorial optimization problems (COPs) are critical to applications across logistics, VLSI design, and scientific discovery, yet remain challenging due to their NP-hard nature. Ising model-based annealers have emerged as promising candidates for solving COPs through probabilistic computing. However, CMOS-based Ising implementations still face barriers in scalability, energy efficiency, and hardware cost. This work presents a compact digital compute-in-memory (DCIM) Ising annealer that overcomes these limitations through several co-optimized algorithm-hardware innovations. A hierarchical clustering approach and a compact weight mapping scheme are introduced to reduce the required hardware cost. Furthermore, we utilize intrinsic process variations in SRAM bitcells to generate random probabilistic bits via pseudo-read operations, enabling an area- and energy-efficient realization of the annealing process without additional random number generators. The fabricated chip, implemented in 28 nm CMOS and featuring a 6 Kb DCIM SRAM array, successfully solves 96-city Traveling Salesman Problem (TSP) instances with time-to-solution of 620 µs and energy consumption of 961 nJ. Compared to prior hardware-based TSP solvers, our solution achieves a 15× to 572× improvement in the hardware cost ratio, validating the effectiveness of our architecture. This work demonstrates the feasibility of large-scale, real-time, and low-cost Ising annealing for combinatorial optimization on digital CMOS platforms.</p>

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A compact digital compute-in-memory Ising annealer with probabilistic SRAM bit in 28 nm for travelling salesman problem

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年3月25日

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  • Yuyao Kong,
  • Anni Lu,
  • Haomei Liu,
  • Vaidehi Garg,
  • Roham Wahabzada,
  • Hai Li,
  • Ian Young,
  • Shimeng Yu

摘要

Combinatorial optimization problems (COPs) are critical to applications across logistics, VLSI design, and scientific discovery, yet remain challenging due to their NP-hard nature. Ising model-based annealers have emerged as promising candidates for solving COPs through probabilistic computing. However, CMOS-based Ising implementations still face barriers in scalability, energy efficiency, and hardware cost. This work presents a compact digital compute-in-memory (DCIM) Ising annealer that overcomes these limitations through several co-optimized algorithm-hardware innovations. A hierarchical clustering approach and a compact weight mapping scheme are introduced to reduce the required hardware cost. Furthermore, we utilize intrinsic process variations in SRAM bitcells to generate random probabilistic bits via pseudo-read operations, enabling an area- and energy-efficient realization of the annealing process without additional random number generators. The fabricated chip, implemented in 28 nm CMOS and featuring a 6 Kb DCIM SRAM array, successfully solves 96-city Traveling Salesman Problem (TSP) instances with time-to-solution of 620 µs and energy consumption of 961 nJ. Compared to prior hardware-based TSP solvers, our solution achieves a 15× to 572× improvement in the hardware cost ratio, validating the effectiveness of our architecture. This work demonstrates the feasibility of large-scale, real-time, and low-cost Ising annealing for combinatorial optimization on digital CMOS platforms.