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<p>This work presents a novel Dual-Bit Ferroelectric Field-Effect Transistor (FeFET) structure that enables localized control of the ferroelectric (FE) layer through a segmented metal gate. This design allows for independent domain switching in distinct regions of the FE material, enabling the memory cell to store two discrete bits while maintaining robust read margins. Crucially, this approach eliminates the need for complex pulsing schemes, such as staircase write voltage pulses, which are typically required for multi-level cell (MLC) FeFETs. We demonstrate the functionality of this device through comprehensive TCAD simulations of read and write operations, considering both process variations and stochastic domain switching behavior. The device achieves a large memory window of 1.61 V even with reduced Program/Erase (P/E) voltages of ±3.3 V and a pulse duration of 1 μs–considerably improving efficiency and endurance. In contrast, conventional FeFETs require higher write voltages (i.e., ±4 V for 10 μs), which accelerate the underlying defect and trap generation, resulting in limited endurance. Our dual-bit design holds the potential for extending the endurance of FeFET-based crossbar arrays, which are crucial for AI accelerators. By effectively doubling the storage capacity, this approach reduces the frequency of weight reprogramming, addressing a key limitation in existing compute-in-memory architectures.</p>

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Dual-Bit FeFET for enhanced storage and endurance

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2025年7月3日

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  • Mahdi Benkhelifa,
  • Simon Thomann,
  • Kai Ni,
  • Hussam Amrouch

摘要

This work presents a novel Dual-Bit Ferroelectric Field-Effect Transistor (FeFET) structure that enables localized control of the ferroelectric (FE) layer through a segmented metal gate. This design allows for independent domain switching in distinct regions of the FE material, enabling the memory cell to store two discrete bits while maintaining robust read margins. Crucially, this approach eliminates the need for complex pulsing schemes, such as staircase write voltage pulses, which are typically required for multi-level cell (MLC) FeFETs. We demonstrate the functionality of this device through comprehensive TCAD simulations of read and write operations, considering both process variations and stochastic domain switching behavior. The device achieves a large memory window of 1.61 V even with reduced Program/Erase (P/E) voltages of ±3.3 V and a pulse duration of 1 μs–considerably improving efficiency and endurance. In contrast, conventional FeFETs require higher write voltages (i.e., ±4 V for 10 μs), which accelerate the underlying defect and trap generation, resulting in limited endurance. Our dual-bit design holds the potential for extending the endurance of FeFET-based crossbar arrays, which are crucial for AI accelerators. By effectively doubling the storage capacity, this approach reduces the frequency of weight reprogramming, addressing a key limitation in existing compute-in-memory architectures.