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<p>Two-dimensional (2D) semiconductors have emerged as strong candidates for beyond-silicon electronics. Their integration into complementary metal–oxide–semiconductor (CMOS) technologies, however, requires both n- and p-type field-effect transistors with competitive performance, scalability and reliability. Although n-type devices remain more mature, p-type 2D field-effect transistors are beginning to support complementary circuits and monolithic three-dimensional integration. This Review examines the physical and technological factors governing CMOS-grade parity in p-type 2D field-effect transistors. Emphasis is placed on contact engineering, including Schottky barrier control, contact scaling and edge-contact strategies compatible with advanced technology nodes. The Review also considers top-gate integration, threshold-voltage engineering for circuit design, and reliability evaluation for scaled devices. Channel growth, selective doping and defect reduction are discussed as essential materials and process requirements for manufacturable technologies. Finally, reporting protocols are outlined to enable consistent benchmarking across studies and to guide scalable complementary and vertically integrated 2D electronics.</p>

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p-Type 2D transistors from contact physics to complementary integration

  • 期刊论文

  • 发表日期：

    2026年6月18日

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  • Saptarshi Das

摘要

Two-dimensional (2D) semiconductors have emerged as strong candidates for beyond-silicon electronics. Their integration into complementary metal–oxide–semiconductor (CMOS) technologies, however, requires both n- and p-type field-effect transistors with competitive performance, scalability and reliability. Although n-type devices remain more mature, p-type 2D field-effect transistors are beginning to support complementary circuits and monolithic three-dimensional integration. This Review examines the physical and technological factors governing CMOS-grade parity in p-type 2D field-effect transistors. Emphasis is placed on contact engineering, including Schottky barrier control, contact scaling and edge-contact strategies compatible with advanced technology nodes. The Review also considers top-gate integration, threshold-voltage engineering for circuit design, and reliability evaluation for scaled devices. Channel growth, selective doping and defect reduction are discussed as essential materials and process requirements for manufacturable technologies. Finally, reporting protocols are outlined to enable consistent benchmarking across studies and to guide scalable complementary and vertically integrated 2D electronics.